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Macros</h2></td></tr>
<tr class="memitem:gada15711b613febaabed053cffec66e57"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__gpio__api.html#gada15711b613febaabed053cffec66e57">XGPIO_L_H</a></td></tr>
<tr class="memdesc:gada15711b613febaabed053cffec66e57"><td class="mdescLeft">&#160;</td><td class="mdescRight">by using protection macros  <a href="group__gpio__api.html#gada15711b613febaabed053cffec66e57">More...</a><br/></td></tr>
<tr class="separator:gada15711b613febaabed053cffec66e57"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga8929998b33d1d66fe8eaa7f454a05ca6"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__gpio__api.html#ga8929998b33d1d66fe8eaa7f454a05ca6">XGPIO_CHAN_OFFSET</a>&#160;&#160;&#160;8</td></tr>
<tr class="memdesc:ga8929998b33d1d66fe8eaa7f454a05ca6"><td class="mdescLeft">&#160;</td><td class="mdescRight">Channel offeset.  <a href="group__gpio__api.html#ga8929998b33d1d66fe8eaa7f454a05ca6">More...</a><br/></td></tr>
<tr class="separator:ga8929998b33d1d66fe8eaa7f454a05ca6"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaac0c290f448e3f86b01f5fcbaa2fff08"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__gpio__api.html#gaac0c290f448e3f86b01f5fcbaa2fff08">XGpio_In32</a>&#160;&#160;&#160;Xil_In32</td></tr>
<tr class="memdesc:gaac0c290f448e3f86b01f5fcbaa2fff08"><td class="mdescLeft">&#160;</td><td class="mdescRight">Input Operations.  <a href="group__gpio__api.html#gaac0c290f448e3f86b01f5fcbaa2fff08">More...</a><br/></td></tr>
<tr class="separator:gaac0c290f448e3f86b01f5fcbaa2fff08"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga2d9bfd9cb86f240e7c57a6f9f0728ba7"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__gpio__api.html#ga2d9bfd9cb86f240e7c57a6f9f0728ba7">XGpio_Out32</a>&#160;&#160;&#160;Xil_Out32</td></tr>
<tr class="memdesc:ga2d9bfd9cb86f240e7c57a6f9f0728ba7"><td class="mdescLeft">&#160;</td><td class="mdescRight">Output Operations.  <a href="group__gpio__api.html#ga2d9bfd9cb86f240e7c57a6f9f0728ba7">More...</a><br/></td></tr>
<tr class="separator:ga2d9bfd9cb86f240e7c57a6f9f0728ba7"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga2cd75ed11bd48af96704b073fa65ef22"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__gpio__api.html#ga2cd75ed11bd48af96704b073fa65ef22">XGpio_WriteReg</a>(BaseAddress, RegOffset, Data)&#160;&#160;&#160;<a class="el" href="group__gpio__api.html#ga2d9bfd9cb86f240e7c57a6f9f0728ba7">XGpio_Out32</a>((BaseAddress) + (RegOffset), (u32)(Data))</td></tr>
<tr class="memdesc:ga2cd75ed11bd48af96704b073fa65ef22"><td class="mdescLeft">&#160;</td><td class="mdescRight">Performs a 32-bit write to a GPIO register.  <a href="group__gpio__api.html#ga2cd75ed11bd48af96704b073fa65ef22">More...</a><br/></td></tr>
<tr class="separator:ga2cd75ed11bd48af96704b073fa65ef22"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga7199da4092b92413af00c613c8cffa57"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__gpio__api.html#ga7199da4092b92413af00c613c8cffa57">XGpio_ReadReg</a>(BaseAddress, RegOffset)&#160;&#160;&#160;<a class="el" href="group__gpio__api.html#gaac0c290f448e3f86b01f5fcbaa2fff08">XGpio_In32</a>((BaseAddress) + (RegOffset))</td></tr>
<tr class="memdesc:ga7199da4092b92413af00c613c8cffa57"><td class="mdescLeft">&#160;</td><td class="mdescRight">Reads a value from a GPIO register.  <a href="group__gpio__api.html#ga7199da4092b92413af00c613c8cffa57">More...</a><br/></td></tr>
<tr class="separator:ga7199da4092b92413af00c613c8cffa57"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">Registers</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>Register offsets for this device. </p>
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<tr class="memitem:ga1712704f3a009d03d0b3201c90259793"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__gpio__api.html#ga1712704f3a009d03d0b3201c90259793">XGPIO_DATA_OFFSET</a>&#160;&#160;&#160;0x0</td></tr>
<tr class="memdesc:ga1712704f3a009d03d0b3201c90259793"><td class="mdescLeft">&#160;</td><td class="mdescRight">Data register for 1st channel.  <a href="group__gpio__api.html#ga1712704f3a009d03d0b3201c90259793">More...</a><br/></td></tr>
<tr class="separator:ga1712704f3a009d03d0b3201c90259793"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gafcefd582c52e56dc7c438a72dfa95546"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__gpio__api.html#gafcefd582c52e56dc7c438a72dfa95546">XGPIO_TRI_OFFSET</a>&#160;&#160;&#160;0x4</td></tr>
<tr class="memdesc:gafcefd582c52e56dc7c438a72dfa95546"><td class="mdescLeft">&#160;</td><td class="mdescRight">I/O direction reg for 1st channel.  <a href="group__gpio__api.html#gafcefd582c52e56dc7c438a72dfa95546">More...</a><br/></td></tr>
<tr class="separator:gafcefd582c52e56dc7c438a72dfa95546"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gae85b884d1fb9ac4c874dd597b1a049b6"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__gpio__api.html#gae85b884d1fb9ac4c874dd597b1a049b6">XGPIO_DATA2_OFFSET</a>&#160;&#160;&#160;0x8</td></tr>
<tr class="memdesc:gae85b884d1fb9ac4c874dd597b1a049b6"><td class="mdescLeft">&#160;</td><td class="mdescRight">Data register for 2nd channel.  <a href="group__gpio__api.html#gae85b884d1fb9ac4c874dd597b1a049b6">More...</a><br/></td></tr>
<tr class="separator:gae85b884d1fb9ac4c874dd597b1a049b6"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gac881efa0580f36e99ab03230b26ca2e2"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__gpio__api.html#gac881efa0580f36e99ab03230b26ca2e2">XGPIO_TRI2_OFFSET</a>&#160;&#160;&#160;0xC</td></tr>
<tr class="memdesc:gac881efa0580f36e99ab03230b26ca2e2"><td class="mdescLeft">&#160;</td><td class="mdescRight">I/O direction reg for 2nd channel.  <a href="group__gpio__api.html#gac881efa0580f36e99ab03230b26ca2e2">More...</a><br/></td></tr>
<tr class="separator:gac881efa0580f36e99ab03230b26ca2e2"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga389241f63fd0ce9af2c1f6dc0f69dcb3"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__gpio__api.html#ga389241f63fd0ce9af2c1f6dc0f69dcb3">XGPIO_GIE_OFFSET</a>&#160;&#160;&#160;0x11C</td></tr>
<tr class="memdesc:ga389241f63fd0ce9af2c1f6dc0f69dcb3"><td class="mdescLeft">&#160;</td><td class="mdescRight">Glogal interrupt enable register.  <a href="group__gpio__api.html#ga389241f63fd0ce9af2c1f6dc0f69dcb3">More...</a><br/></td></tr>
<tr class="separator:ga389241f63fd0ce9af2c1f6dc0f69dcb3"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga6cbde8210cb1476b67ca87eccacbc2ed"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__gpio__api.html#ga6cbde8210cb1476b67ca87eccacbc2ed">XGPIO_ISR_OFFSET</a>&#160;&#160;&#160;0x120</td></tr>
<tr class="memdesc:ga6cbde8210cb1476b67ca87eccacbc2ed"><td class="mdescLeft">&#160;</td><td class="mdescRight">Interrupt status register.  <a href="group__gpio__api.html#ga6cbde8210cb1476b67ca87eccacbc2ed">More...</a><br/></td></tr>
<tr class="separator:ga6cbde8210cb1476b67ca87eccacbc2ed"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga4f62e4ffa9e47cd55133c583134f4f57"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__gpio__api.html#ga4f62e4ffa9e47cd55133c583134f4f57">XGPIO_IER_OFFSET</a>&#160;&#160;&#160;0x128</td></tr>
<tr class="memdesc:ga4f62e4ffa9e47cd55133c583134f4f57"><td class="mdescLeft">&#160;</td><td class="mdescRight">Interrupt enable register.  <a href="group__gpio__api.html#ga4f62e4ffa9e47cd55133c583134f4f57">More...</a><br/></td></tr>
<tr class="separator:ga4f62e4ffa9e47cd55133c583134f4f57"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">Interrupt Status and Enable Register bitmaps and masks</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>Bit definitions for the interrupt status register and interrupt enable registers. </p>
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<tr class="memitem:ga421755999f173a708b8254bb9cdc9b62"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__gpio__api.html#ga421755999f173a708b8254bb9cdc9b62">XGPIO_IR_MASK</a>&#160;&#160;&#160;0x3</td></tr>
<tr class="memdesc:ga421755999f173a708b8254bb9cdc9b62"><td class="mdescLeft">&#160;</td><td class="mdescRight">Mask of all bits.  <a href="group__gpio__api.html#ga421755999f173a708b8254bb9cdc9b62">More...</a><br/></td></tr>
<tr class="separator:ga421755999f173a708b8254bb9cdc9b62"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga216177d9cad31a8fa22c4114c754f3ae"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__gpio__api.html#ga216177d9cad31a8fa22c4114c754f3ae">XGPIO_IR_CH1_MASK</a>&#160;&#160;&#160;0x1</td></tr>
<tr class="memdesc:ga216177d9cad31a8fa22c4114c754f3ae"><td class="mdescLeft">&#160;</td><td class="mdescRight">Mask for the 1st channel.  <a href="group__gpio__api.html#ga216177d9cad31a8fa22c4114c754f3ae">More...</a><br/></td></tr>
<tr class="separator:ga216177d9cad31a8fa22c4114c754f3ae"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga202cdf1a14179cd31df27346a55dced4"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__gpio__api.html#ga202cdf1a14179cd31df27346a55dced4">XGPIO_IR_CH2_MASK</a>&#160;&#160;&#160;0x2</td></tr>
<tr class="memdesc:ga202cdf1a14179cd31df27346a55dced4"><td class="mdescLeft">&#160;</td><td class="mdescRight">Mask for the 2nd channel.  <a href="group__gpio__api.html#ga202cdf1a14179cd31df27346a55dced4">More...</a><br/></td></tr>
<tr class="separator:ga202cdf1a14179cd31df27346a55dced4"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">Global Interrupt Enable Register bitmaps and masks</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>Bit definitions for the Global Interrupt Enable register </p>
</div></td></tr>
<tr class="memitem:ga0b576e472f8ad06f166d9107de3b0348"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__gpio__api.html#ga0b576e472f8ad06f166d9107de3b0348">XGPIO_GIE_GINTR_ENABLE_MASK</a>&#160;&#160;&#160;0x80000000</td></tr>
<tr class="memdesc:ga0b576e472f8ad06f166d9107de3b0348"><td class="mdescLeft">&#160;</td><td class="mdescRight">Mask for Global Interrupt.  <a href="group__gpio__api.html#ga0b576e472f8ad06f166d9107de3b0348">More...</a><br/></td></tr>
<tr class="separator:ga0b576e472f8ad06f166d9107de3b0348"><td class="memSeparator" colspan="2">&#160;</td></tr>
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